1. Field of the Invention
The present invention relates to digital image decoding, and more specifically to image compression in digital image decoding, in order to reduce the required storage capacity of a frame memory, and further to reduce the deterioration of the output image which may be caused by the compression algorithm by adaptively applying compression based upon the size of the image data. The digital image decoding should be implemented in a digital image system such as digital CATV and digital broadcasting.
2. Discussion of the Prior Art
FIGS. 54 and 55 show the block diagram and external memory map of a prior art image processing apparatus, namely the SGS-Thomson, STi3500, described in a manual issued by SGS-Thomson Microelectronics.
In FIG. 54, reference numeral 501 denotes a microcomputer interface; 502 an FIFO (First-in First-out) memory; 503 a start code detection unit; 504 a memory I/O (Input/Output) unit; 505 a variable-length decoder unit; 506 a decoder unit; 507 a display processing unit; 508 an external memory; 550 a micro-computer interface line; 551 a micro-computer bus; 552 data lines; 553 data lines; 554 an external memory bus; and 555 an input/output line.
In FIG. 55, reference numeral 601 denotes a bit buffer; 602 an on-screen display (OSD) memory; 603 a first predictive frame memory; 604 a second predictive frame memory; and 605 a display frame memory.
The operation of the prior art apparatus will now be described. Encoded data accumulated in the bit buffer 601 of the external memory 508 is fed to the start code detection unit 504 through the external memory bus 554 wherein the start code of the encoded data is detected. After the start code has been detected, the encoded data portion following the start code is supplied to the variable-length decoder unit 505 through the FIFO memory 502, wherein the encoded data portion is subjected to variable-length decoding. The variable-length decoded data is then processed and subjected to image decoding by the decoder unit 506. The decoded image is written into the external memory 508 through the memory I/O unit 504.
The external memory 508 includes the first predictive frame memory 603, the second predictive frame memory 604 and the display frame memory 605. Each of the memories 603, 604, 605 stores decoded images. Image data used to predict the other frames is written into the first or second predictive frame memory 603, 604. Image data used only for driving the display is written into the display frame memory 605.
The data written into the display frame memory 605 is then read out in synchronism with signals such as the horizontal/vertical synchronizing signals in TV scenes and outputted to the display processing unit 507 through the external memory bus 554.
Alphanumeric character data to be displayed in the OSD (on-screen display) memory 602 of the external memory 508 may be accessed as in the display frame memory area 605 and then supplied to the display processing unit 507 through the external memory bus 554. If the data in the OSD memory 602 is valid, the display processing unit 507 overlays the data from the OSD memory 602 onto the data read out from the display frame memory 605 and externally outputs the overlaid data.
In such a manner, the prior art displays an image on the display data that has been stored in the external memory 508.
In the aforementioned digital image decoding apparatus of the prior art, the external memory 508 must store all the data required by the decoding step. More particularly, if data that spans adjacent frames is to be encoded, all the data of other related frames used to encode the one frame have to be stored in the external memory 508 to successfully decode the image data of that frame.
Therefore, the prior art decoding technique requires a huge data storage device to store the related frames. The large capacity required by the external memory 508 is a clear disadvantage because of the large size and cost of constructing such a memory.